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De Morgans Law

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    Hi
    I am struggling with the diagram of this question. Can anyone help? I would have loaded my diagram but unsure how to do it. This is the question:

    Starting with the following statement (A+B).(A+C), show how this can be implemented using NAND gates using DeMorgans law.

    After doubly negating, I obtained (A.B) + (A.C). And this is where I get stuck.

    Please help. I have a deadline looming this week.

    Cheers
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    Better asked in the Computing forum.

    You can factorise to A.(B+C)

    Do you know the NAND equivalnets for OR and AND? If so use them then delete any consecutive NOTs.
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    (Original post by teachercol)
    Better asked in the Computing forum.

    You can factorise to A.(B+C)

    Do you know the NAND equivalnets for OR and AND? If so use them then delete any consecutive NOTs.
    Not totally sure. Thanks. Do you have an idea of what the diagram would look like? Thanks
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    Its a standard bit of digital electronics. See here for example

    http://www.kpsec.freeuk.com/gates.htm

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