whats there email?(Original post by ryanroks1)
I didn't sit F452 yesterday but it might be worth emailing OCR if you feel there were any problems. I emailed them last year about that 'FreeMeals' variable error and they responded with a pretty lengthy letter that did mention complaints are taken into account during the awarding process (ie setting grade boundaries).
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OCR A2 Computing F453 Official Thread 22/06/2016 Exam Discussion watch
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- 15-06-2016 12:45
(Original post by MrSplash)
whats there email? -
geekface98
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- 15-06-2016 14:18
I've gotten this back from them....
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Dear Mohamed
OCR AssessmentsThank you for your emails earlier today.We have a formal procedure for dealing with all such feedback. We are progressing the issues you have raised through that route and we will be in contact with you again shortly.
Yours sincerely
Customer Service Team -
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- 15-06-2016 14:37
(Original post by geekface98)
I've gotten this back from them....
....
Dear Mohamed
OCR AssessmentsThank you for your emails earlier today.We have a formal procedure for dealing with all such feedback. We are progressing the issues you have raised through that route and we will be in contact with you again shortly.
Yours sincerely
Customer Service Team -
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- 15-06-2016 14:38
(Original post by geekface98)
I've gotten this back from them....
....
Dear Mohamed
OCR AssessmentsThank you for your emails earlier today.We have a formal procedure for dealing with all such feedback. We are progressing the issues you have raised through that route and we will be in contact with you again shortly.
Yours sincerely
Customer Service Team -
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- 15-06-2016 14:39
Has anyone seen any questions on MFQ(Multi-level feedback queues) in past papers?
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geekface98
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- 15-06-2016 14:47
(Original post by Aydin7)
Has anyone seen any questions on MFQ(Multi-level feedback queues) in past papers? -
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- 15-06-2016 14:50
It's one of the scheduling algorithms(3.1.2)
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- 15-06-2016 16:09
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- 15-06-2016 16:25
(Original post by ExamBuddy101)
Never heard of it either. Is it from one of them funny textbooks? Some are too detailed and go into greater detail than the specification requires.
I still have 5 PP to do so I wasn't sure if it came up on any of those.
Thanks for the help. -
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- 15-06-2016 17:07
(Original post by pragyas265)
OCR grade boundaries were really low last year. You could lose approximately 40 marks and still get an A.
Btw, what did you get for the question where you had to calculate the size of the file? It was in question 1, -
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- 15-06-2016 18:59
**** ocr -
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- 15-06-2016 19:00
(Original post by geekface98)
It was 67 for an A last year... I got 66 -
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- 15-06-2016 19:25
I have a question in relation to RISC & CISC. Here is my understanding of the terms, roughly:
RISC- Relatively small instruction set, complete given task in 1 clock cycle, each instruction performs a relatively simple operation. 1 CISC instruction = many RISC instructions
CISC - 100's variable format instructions - many include low-level operations to complete a single instruction. There are a wide variety of addressing modes which can include array processing instructions. Complex & can take dozens of clock cycles to complete. More than 1 register sets may be used.
However, there are some inconsistencies in the mark schemes which I have attached and I am a bit confused. Thoughts?
2011-06-F453: 3) b) i) State 3 features of CISC architecture & ii) Disadvantage of CISC compared to RISC, other than cost
2010-01-F453: 3) b) i) Complete the table & ii) Compare the number of machine cycles used by RISC & CISC to complete a single instruction.
Attachment 550813550815
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ryanroks1
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- 16-06-2016 00:20
(Original post by ExamBuddy101)
I have a question in relation to RISC & CISC. Here is my understanding of the terms, roughly:
RISC- Relatively small instruction set, complete given task in 1 clock cycle, each instruction performs a relatively simple operation. 1 CISC instruction = many RISC instructions
CISC - 100's variable format instructions - many include low-level operations to complete a single instruction. There are a wide variety of addressing modes which can include array processing instructions. Complex & can take dozens of clock cycles to complete. More than 1 register sets may be used.
However, there are some inconsistencies in the mark schemes which I have attached and I am a bit confused. Thoughts?
2011-06-F453: 3) b) i) State 3 features of CISC architecture & ii) Disadvantage of CISC compared to RISC, other than cost
2010-01-F453: 3) b) i) Complete the table & ii) Compare the number of machine cycles used by RISC & CISC to complete a single instruction.
Attachment 550813550815
To be safe, if the question did come up, it might be best we email OCR with those screenshots to confirm if either would be accepted given they clearly don't even know what's right! -
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- 16-06-2016 08:16
(Original post by ryanroks1)
Just a prime example of OCR's inadequacies. If a question comes up on it this year, I'm going to stick with the fact RISC singular instructions can be executed in a single cycle, but in order to perform tasks, may need to be joined together. However, one CISC instruction may perform a full task but can take multiple cycles to do so. I think the mark scheme messed up on that one...
To be safe, if the question did come up, it might be best we email OCR with those screenshots to confirm if either would be accepted given they clearly don't even know what's right!I think each "instruction" takes a single cycle in each processor, however a "task" may be made of multiple instructions in RISC. OCR seems to use the terms interchangeably (stupid I know).
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- 16-06-2016 09:31
(Original post by ryanroks1)
Just a prime example of OCR's inadequacies. If a question comes up on it this year, I'm going to stick with the fact RISC singular instructions can be executed in a single cycle, but in order to perform tasks, may need to be joined together. However, one CISC instruction may perform a full task but can take multiple cycles to do so. I think the mark scheme messed up on that one...
To be safe, if the question did come up, it might be best we email OCR with those screenshots to confirm if either would be accepted given they clearly don't even know what's right!Last edited by ExamBuddy101; 16-06-2016 at 09:35. -
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- 16-06-2016 09:34
(Original post by Jamuk)
Yeah I also get confused on those questionsI think each "instruction" takes a single cycle in each processor, however a "task" may be made of multiple instructions in RISC. OCR seems to use the terms interchangeably (stupid I know).
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- 16-06-2016 10:30
How is everyone feeling about F453? It's getting close now eek
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- 16-06-2016 10:51
F453 June 2012 Q5(c)
Question:
https://gyazo.com/4be2438bdd00b410603bf86f88307bf9
Mark Scheme:
https://gyazo.com/35a616546b5b6120cfebcf5ef2770eab
Can somebody possibly explain this visually with a diagram? I understand how a queue data structure is used briefly and how its uses pointers but in context I'm a little confused. I got the first point but the rest confused me.
Thanks
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