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computer science - pull-up circuit/transistors confusion (basic) Watch

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    is there a reason why x and z get negated and use a p-type transistor (and vice-versa for y)? i'm talking about the first diagram

    thanks in advance for any input
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    is there a reason why x and z get negated and use a p-type transistor (and vice-versa for y)? i'm talking about the first diagram

    thanks in advance for any input


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    managed to find out why..

    tried to do this question though but got stuck on the pull-down part. how do i draw x + y in series with z in parallel (all in one)?
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    As far as logic is concerned, it is purely down to the device manufacturer which type of semiconductor together with physical implementation is employed. Some configurations are more easily fabricated in silicon than others.

    There are many physical reasons why certain configurations are used in some cases and not others - all depends on the intended physical application of the employed device.

    Circuit designers also like flexibility and will choose a device with logic closest (read easiest) fit to their intended application. In which case, manufacturers will offer devices with both inverting and non-inverting inputs for the same application.

    For example, a high fan-out capability (one device driving many inputs) needs to have a low output impedance config' to give a good current driving ability. This is also true for logic devices driving high current items directly - such as LED's or relays etc. In these cases 'open-collectors' are used with NPN devices and therefore are non-inverting because the connected device is turned on when the collector is pulled down. In a purely logic sense with a collector resistor in place, the voltage measured at the collector is inverted w.r.t. the input.

    It all comes down to threshold voltages, the forward-bias voltage needed to turn-on silicon bipolar semiconductors and their minimum base-currents or the minimum gate-source voltage in the case of FET's etc.

    In your case, it's important only so far as knowing the logic for the type of device employed which will tell you whether the device is configured to invert the input or not. The implementation could just as easily be PNP with a collector pull-down device which would logically mean an inverting input. Or NPN with a pull-up device meaning inverting input.

    Does that make more sense?
 
 
 
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