leosco1995
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#1
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I've made this circuit on a breadboard and it works:


(the page I got it from) but I don't understand how exactly it works. I know a transistor is an amplifier and that a larger current flows from the collector to the emitter when some input is given at the base, but that isn't what Q2 is doing in the diagram? And why are Q1 and Q3 NPN transistors while Q2 is PNP?

I just don't understand why the transistors are connected in this fashion and what they are doing..

Help would be appreciated
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Joinedup
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(Original post by leosco1995)
I've made this circuit on a breadboard and it works:


(the page I got it from) but I don't understand how exactly it works. I know a transistor is an amplifier and that a larger current flows from the collector to the emitter when some input is given at the base, but that isn't what Q2 is doing in the diagram? And why are Q1 and Q3 NPN transistors while Q2 is PNP?

I just don't understand why the transistors are connected in this fashion and what they are doing..

Help would be appreciated
Qs1&2 are a complimentary pair of power transistors, a PNP and NPN with similar parameters - you should look up class B & AB amplifier (aka push-pull) e.g. http://www.electronics-tutorials.ws/...ier/amp_6.html

manufacturers produce & market complimentary pairs of transistors e.g. 2n3055 & mj2955 (which are a fairly famous pair) - though this doesn't seem to have been the case with 2n3053 & 2n2905a (though they are kind of similar) so perhaps they're just what the guy had lying around.

additional hint - 2 diodes in series always look like they're there to provide 2x the forward voltage drop of one diode
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uberteknik
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(Original post by leosco1995)
I've made this circuit on a breadboard and it works:


(the page I got it from) but I don't understand how exactly it works. I know a transistor is an amplifier and that a larger current flows from the collector to the emitter when some input is given at the base, but that isn't what Q2 is doing in the diagram? And why are Q1 and Q3 NPN transistors while Q2 is PNP?

I just don't understand why the transistors are connected in this fashion and what they are doing..

Help would be appreciated
There is a lot more going on with this circuit than at first glance.

The output pair are both emitter followers and each conducts only on part of the input waveform whilst the other is in cut-off.

Q1 and Q2 are biased to operate in class B by D1 and D2 which provides a forward voltage drop of around 1.4V between the two bases in order to overlap conduction as the input voltage approaches the cut-off for both output devices. This avoids the dreaded 'crossover' distortion which occurs when the input voltage is less than the forward Vbe voltage required to overcome the energy band-gap inherent with silicon-semiconductor devices.

Q3 is also an emitter follower but is biased to be in permanent conduction (class A). The circuit is therefore designated class AB as a hybrid between the two.

R6 provides a 'bootstrap' for biasing Q3: When biasing an emitter follower, the base must be biased into conduction and normally, a voltage divider pair of resistors are used for this purpose. Values are chosen so that their parallel impedance is much less than the impedance the input signal would see when presented by the base-emitter impdance alone. i.e. the input impedance is dominated by the voltage divider and not that of the semiconductor.

However, that means the signal source is loaded by the bias resistors of Q3 which must be low values in order to provide the high drive current necessary for the current gain to subsequently drive the output pair of semi-conductors.

In a bootstrapped feedback arrangement (as with this circuit), part of the quiescent current flowing through the emitter-collectors of both Q1 and Q2 is used to ensure that the loading (shunt) impedance of the bias network (R5, R6) is much larger at signal frequencies than under purely d.c. conditions and R6 'appears' to have an a.c. value many times its d.c. resistance would suggest such that the base impedance looking into the base of Q3 becomes dominant. (NB. the capacitors C1 and C2 are essential to block d.c. that would otherwise destroy circuit operation).

The output pair must be 'matched' for gain characteristics or distortion of the output signal will result.

The circuit could also suffers from thermal instability as the output pair heats up under power conditions driving the loudspeaker load, the base-emitter voltage drop (0.7V for silicon devices) increases by around 2.1mV/oC and the collector current increases by a factor of 10 for every 60mV increase in base-emitter voltage.

This means that as the output transistors heat up, their current gain will increase thus causing gain instability and ultimately (if left unchecked) thermal-runaway will destroy the output pair. This outcome increases significantly if the loudspeaker load impedance is reduced below 8ohms (e.g. a 4 ohm loudspeaker is used).

Adequate heat-sinking is definitely advised. Mounting the bias diodes close to the output pair on the same heatsink, will circumvent some of the thermal instability by causing the diodes to thermally track the output pair and thus alter biasing to compensate. That said, the two 3.3 ohm emitter resistors of Q1 and Q2 will limit the maximum available output current and in so doing, will also use reduce overall efficiency by at least 25% at full output (8 ohm loudspeaker) for the privilege - which kinda defeats the object of using class B from a power efficiency point of view but useful to limit heat dissipation in the output pair. A lower impedance 4 ohm loudspeaker will decrease efficiency even further (approaching 50% @ full output).

Correct values for C1 and C2 need to be chosen. As it stands, they do nothing other than block d.c. which can be accomplished by far smaller components. The values used for C1 and C2 in this circuit are huge and unnecessary - as Joinedup pointed out, seems like the designer grabbed anything to hand rather than using calculation for optimum performance.

The power supply needs to be load tolerant (no voltage droop under load) to prevent an inadvertent signal feedback path via the supply or h.f. oscillation will result and destroy both circuit operation and the output transistors!

As I said, there is more to this circuit than at first glance.
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