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    Hi,

    This is a picture of a JFET



    How do we know the bias of the drain, source and gate? Shouldn't the drain be forward-bias because it is connected to the +ve terminal of the battery?
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    (Original post by leosco1995)
    Hi,

    This is a picture of a JFET



    How do we know the bias of the drain, source and gate? Shouldn't the drain be forward-bias because it is connected to the +ve terminal of the battery?
    The operation of a FET is very different to that of a bi-polar device and operation must not be thought of in the same terms.

    NB the potential difference applied to the PN or NP junction is critical to understanding whether the junction is forward or reverse biased because of the majority and minority charge carriers within each region. You must fully understand the semiconductor PN junction diode operation before you can proceed.

    For clarity: a PN junction will be forward biased if the P side of the junction is more +ve than the N side enough to overcome the potential barrier created with the junction depletion region.

    Operation of the JFET (sometimes called JUGFET) relies on a charge carrier conduction 'channel' (between the drain and source), which is sandwiched between two gate regions on either side.

    In this physical arrangement, the PN junction depletion regions can be made to extend further into the N region or contract towards the P region by application of a voltage to the gate w.r.t. the source (biasing).

    i.e. the extent of the depletion regions on either side of the N channel conduction path between the drain and source, can be manipulated to control the effective cross sectional area of the conduction channel within the N substrate between the source and drain..

    Since current is the rate of change of charge, than altering the dimensions of the conduction channel (by changing the voltage of the gate) will change the rate at which charge can flow between the drain and source.

    i.e. An applied reverse bias between the gate and the channel has the effect of widening the depletion regions local to the PN junctions and consequently, the width of the depletion regions can be controlled.

    The diagram on it's own is for a specific case of biasing arrangement only and is meant to illustrate part of the operation of a JFET under a very specific limited single case of biasing condition.

    The diagram shows the gate and source linked via a conductor to give clarity that all voltages are shown with respect to the source.

    It therefore shows the PN junction region of the gate-drain reverse biased. In that arrangement, electrons will be driven away from the junction region on the p-side and will therefore creates a larger depletion region across the junction. The conductance of the channel between the drain and source must therefore decrease.

    Very little current (leakage current measured nA or less) will flow between the gate and drain.

    Similarly, the gate-source P and N regions respectively, are held at the same potential by the conductor linking them and because they are at the same potential, again very little current will flow between them.

    This all serves to show that the gate voltage controls the conductance of the N channel and hence the critical characteristics of the JFET are stated as:

    g_m = \mathrm { \ mutual \ conductance \ or \ transconductance \ } = \frac{\Delta I_D}{\Delta V_{GS}}\rvert V_{DS} \mathrm {\ constant}

    r_D = \mathrm { \ drain \ resistance \ } = \frac{\Delta V_{DS}}{\Delta I_D}\rvert V_{GS} \mathrm {\ constant}

    \mu = \mathrm { \ amplification \ factor \ } = \frac{\Delta V_{DS}}{\Delta V_{GS}}\rvert V_{GS} \mathrm {\ constant} = r_Dg_m
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    (Original post by leosco1995)

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    Hi.

    I noticed you have not replied to my answer. Have you resolved your understanding for the operation of the JFET and why the gate-drain PN junction is reverse biased when the drain is more +ve than the gate?

    If you want/need further clarification please ask.
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    Yeah, I got how it operates. Sorry for the late response. There's just 2 things I don't get:

    The diagram shows the gate and source linked via a conductor to give clarity that all voltages are shown with respect to the source.

    It therefore shows the PN junction region of the gate-drain reverse biased
    . In that arrangement, electrons will be driven away from the junction region on the p-side and will therefore creates a larger depletion region across the junction. The conductance of the channel between the drain and source must therefore decrease.
    Still a bit confused. If all voltages are taken with respect from the source then is the source +ve or -ve? It's connected to ground. And how does this relate to the gate-drain bias?

    I get how the depletion width can be controlled and how that affects the current but the bias of these 3 (bias, drain and source) still confuse me.
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    (Original post by leosco1995)
    Yeah, I got how it operates. Sorry for the late response. There's just 2 things I don't get:


    Still a bit confused. If all voltages are taken with respect from the source then is the source +ve or -ve? It's connected to ground. And how does this relate to the gate-drain bias?

    I get how the depletion width can be controlled and how that affects the current but the bias of these 3 (bias, drain and source) still confuse me.
    Taking the source as the reference is no different to simply saying all other potentials are measured with respect to it. Voltage potentials can thus be higher (more +ve) or lower (more -ve) than the source as the 0V reference point.

    Conventional current always flows from the higher to the lower potential (opposite to the actual electron charge flow).

    Case 1

    Looking at the diagram, if VS < VG < VD, then

    A potential gradient will exist between the drain and source with the drain at the higher potential.

    the gate to drain PN junction will be reverse biased.
    the gate to source PN junction will be forward biased and current will flow from the gate to the source as a normal silicon diode.

    Case 2

    If VG < VS < VD then

    the gate to drain PN junction will still be reverse biased
    the gate to source PN junction will now also be reverse biased
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    Alright, got it. Thanks
 
 
 
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