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    Hi All,

    I have the following output buffer made of transistors:

    and I need to choose appropiate components and values, using calculations to justify my choice.

    I was thinking of using BC107 and 2N2905A for the NPN and PNP respectively. Or alternatively 2N4033 and 2N2222A. But what calculations/formulas can i do to justify my selection to make sure they are ok to be used.

    Also for the resistors R1 and R3 i was thinking of setting them as 3.3k ohm. Can anyone help suggest values for R2 and R4 and calculations?

    TR2 essentially short circuits when turned on to provide an override.

    The output I believe varies from 0 to -10V, as does the input. I think the overide input is 15V.

    Any help will be greatly appreciated! Thanks!
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    (Original post by northy16)
    Hi All,

    I have the following output buffer made of transistors:

    and I need to choose appropiate components and values, using calculations to justify my choice.

    I was thinking of using BC107 and 2N2905A for the NPN and PNP respectively. Or alternatively 2N4033 and 2N2222A. But what calculations/formulas can i do to justify my selection to make sure they are ok to be used.

    Also for the resistors R1 and R3 i was thinking of setting them as 3.3k ohm. Can anyone help suggest values for R2 and R4 and calculations?

    TR2 essentially short circuits when turned on to provide an override.

    The output I believe varies from 0 to -10V, as does the input. I think the overide input is 15V.

    Any help will be greatly appreciated! Thanks!
    This asks more questions than provides answers:

    It's clearly a simple logic function which holds the o/p at just below 0V (high) when the control switch is inactive also at 0V (high). Any signal present at the i/p will be overridden in this state.

    The circuit therefore represents a tri-state buffer with active low control:




    When the control switch is held at the -ve supply rail -15V (low), the o/p logic follows the i/p logic signal.

    So the important questions before calculations can be made and components chosen are:

    1) what are the switching threshold voltages? i.e. how critical are they and how close do they need to be to the 0V and -15V rails?

    2) how much drive current can be taken from the i/p signal to activate the first transistor? Are there other components hanging off the preceding drive stage (i/p to this stage) which needs consideration?

    3) how much current does the o/p sink to the next stage? i.e. what is the loading on the o/p device?

    4) Is the switching speed a critical parameter? i.e. rise and fall times and switching frequency?

    5) Are you sure about the logic voltages? +15v will cause a reverse bias across the PNP devices base-emitter junction and hence exceed it's rated breakdown voltage which is likely to destroy the device.

    6) Does the operating environment need consideration? i.e. what environment does this need to operate within?

    7) Is this a one-off proof-of-concept project or is this something that needs to be taken through to production? i.e. is cost a factor in the engineering?
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    (Original post by uberteknik)
    This asks more questions than provides answers:

    It's clearly a simple logic function which holds the o/p at just below 0V (high) when the control switch is inactive also at 0V (high). Any signal present at the i/p will be overridden in this state.

    The circuit therefore represents a tri-state buffer with active low control:




    When the control switch is held at the -ve supply rail -15V (low), the o/p logic follows the i/p logic signal.

    So the important questions before calculations can be made and components chosen are:

    1) what are the switching threshold voltages? i.e. how critical are they and how close do they need to be to the 0V and -15V rails?

    2) how much drive current can be taken from the i/p signal to activate the first transistor? Are there other components hanging off the preceding drive stage (i/p to this stage) which needs consideration?

    3) how much current does the o/p sink to the next stage? i.e. what is the loading on the o/p device?

    4) Is the switching speed a critical parameter? i.e. rise and fall times and switching frequency?

    5) Are you sure about the logic voltages? +15v will cause a reverse bias across the PNP devices base-emitter junction and hence exceed it's rated breakdown voltage which is likely to destroy the device.

    6) Does the operating environment need consideration? i.e. what environment does this need to operate within?

    7) Is this a one-off proof-of-concept project or is this something that needs to be taken through to production? i.e. is cost a factor in the engineering?
    I dont think your assessment of the circuit is quite right. The output buffer is intended to keep the voltage between 0 and 10V. Having a voltage less than 0V is not allowed.

    2) Here is the link to the preceeding drive stage, an integrator. Its output cannot be below 0V and goes into the input of the transistor buffer above. http://imgur.com/hRwOf5F?desktop=1

    6) has to operate between 20 - 55 degrees c but apart from that fairly ordinary environment.

    7) it has to be taken through to production. No budget has been assigned, but be sensible and realistic i.e dont spend £100 on transistors.
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    (Original post by northy16)
    I dont think your assessment of the circuit is quite right. The output buffer is intended to keep the voltage between 0 and 10V. Having a voltage less than 0V is not allowed.
    The buffer supply rails are 0V and -15V according to the schematic you originally posted, or am I not reading that correctly? Hence the absolute maximum output swing must be between 0V and (-15 + VCE) across TR3.

    Given the preceding stage circuit, then the o/p will track the input less a couple of forward bias voltage drops across the base-emitter junctions of TR1 and TR3. i.e. within the maximum range -0.7V to -13.7V or so.

    (Original post by northy16)
    2) Here is the link to the preceeding drive stage, an integrator. Its output cannot be below 0V and goes into the input of the transistor buffer above. http://imgur.com/LTbndPv
    Unless R5 in the linked schematic is a capacitor, this stage cannot be an integrator. However, that does not take into account the input to A1 which may itself be an integrated function.

    Since there is no feedback around IC4, this device performs a threshold comparator function with threshold voltage set by the ratio between R8 and R9. The threshold must therefore be within the range 0V to -10V.

    If the input to A2 is less than the threshold level, then the output of IC4 will saturate to near the +15V supply rail. If the input to this device is greater than the threshold level, the output to IC4 will saturate to near the -15V supply rail.

    IC3 is arranged as a differential amplifier with gain.

    D1 and D2 perform a precedence function such that if the i/p to A2 is below the threshold voltage set by R8/9, then the 'interlock' o/p will be pulled up to the saturated +ve output of IC4 less the forward bias volt drop across D2. i.e. somewhere around +10 to +12V dependent on the devices selected.

    If the i/p to A2 is above the threshold set by R8/9, then the A1 i/p takes precedence and the 'interlock' o/p will track the o/p of IC3 less the forward bias volt drop across D1.

    i.e. the combined function will track the differential input A1 unless it is overridden by the A2 input in which case the output of the following buffer stage will be pulled up to 0V.
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    (Original post by uberteknik)

    It's clearly a simple logic function which holds the o/p at just below 0V (high)
    This is the bit I questioned your assessment, as the output can't go below 0V.

    Also I posted the wrong link before, the integrator circuit has now been posted. The comparator link was for the other question I posted on a different thread..
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    (Original post by northy16)
    This is the bit I questioned your assessment, as the output can't go below 0V.

    Also I posted the wrong link before, the integrator circuit has now been posted. The comparator link was for the other question I posted on a different thread..
    OK. The transistors are arranged as common-collector amplifiers and so the gain will be near unity with a high input impedance and low output impedance.

    My comment re the maximum voltage swings still stands because your circuit indicates supply rails of 0V and -15V so the output cannot exceed these limits.

    You need to check that these are the correctly stated voltages.
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    (Original post by uberteknik)
    OK. The transistors are arranged as common-collector amplifiers and so the gain will be near unity with a high input impedance and low output impedance.

    My comment re the maximum voltage swings still stands because your circuit indicates supply rails of 0V and -15V so the output cannot exceed these limits.

    You need to check that these are the correctly stated voltages.
    Yep, you are right. Those supply rails are correct.

    The reason I was getting confused is because i have a similar circuit but the supply voltages are 0v and +15V. Hence in that instance the output couldnt fall below 0V.
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    (Original post by uberteknik)
    OK.
    Can we start selecting components now?
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    (Original post by uberteknik)

    5) Are you sure about the logic voltages? +15v will cause a reverse bias across the PNP devices base-emitter junction and hence exceed it's rated breakdown voltage which is likely to destroy the device.
    I'm sure it's 15V. With R2 and R4 acting as a potential divider. if R2 is 4.7k ohms and R4 is 15k ohms the base-emitter voltage will be 3.579V which will not exceed the breakdown voltage?
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    (Original post by northy16)
    I'm sure it's 15V. With R2 and R4 acting as a potential divider. if R2 is 4.7k ohms and R4 is 15k ohms the base-emitter voltage will be 3.579V which will not exceed the breakdown voltage?
    OK. I'll have a look at these shortly. Is this for a dissertation or a coursework project or something you have been contracted to do?
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    (Original post by uberteknik)
    OK. I'll have a look at these shortly. Is this for a dissertation or a coursework project or something you have been contracted to do?
    It's work experience task, but it's not a contract for a customer. Just a made up task to see how well I handle it.
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    (Original post by northy16)
    It's work experience task, but it's not a contract for a customer. Just a made up task to see how well I handle it.
    That makes a lot more sense now.

    From what I have seen, there are deliberate errors in the circuits you have provided. Without knowing the purpose of the whole electronics function and a breakdown into block transfer functions, it's impossible to analyse the circuit for error.

    For instance, you posted a circuit for a precision reference function (+/- 10V). The -10V o/p shows at least 2 obvious errors. Further, the series resistor is there to hold the o/p current within specific limits for the device chosen. But the calculation for that current limiting resistor value cannot be performed without knowing exactly the current demanded by the -10V reference load.

    Obvious errors are included in the integrator function you posted. For example, as drawn it will not function as intended: there are resistors in the supply rails to the op-amp. This is simply bad practice, because it deliberately causes noise to appear on the supply input to the device when the load current fluctuates in response to the input signal. This will easily induce unwanted feedback and possibly oscillation. But there is no clue to why the designer thought these were necessary and what it attempts to achieve.

    Another problem with this circuit is the capacitor between the i/p terminals to the op amp. With no feedback path from the output, the open loop differential gain is 10's of thousands and the smallest charge on the capacitor will cause the output to saturate. Further as the input frequency increases, the capacitor will act to tie the inputs together. Common mode bias differences internal to the op-amp will cause a d.c. offset error at the output.

    There are other obvious errors too, like the a/c coupling capacitor to the emitter-follower buffer stage. There is no current path (biasing) for the base of the input device.

    The capacitor and emitter resistor introduces a lower frequency cut-off point, but without knowing the i/p waveform or how critical the frequency response needs to be, the biasing arrangement and passive components cannot be selected.

    There is no indication as to how accurately the buffer needs to track the input etc.

    As you can see from these questions alone, it's impossible to design a circuit without a fully comprehensive understanding of the whole intended circuit function, because each stage interacts and is dependent on both the input and output signals and loadings. Analogue circuit design by necessity is an iterative process.

    I've probably gone as far as I can without significant access to the originator.
 
 
 
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