RISC and CISC, tasks and instructions [OCR F543]

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CervixPounder
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Hey there,

I was doing some practice questions on computer architectures, and I'm not really understanding the difference in OCRs definitions of tasks and instructions.

For example, when told to "Comment on the number of machine cycles used to carry out an instruction, on a RISC and CISC architecture"

The mark scheme says:

"RISC: Each task may take many cycles."

"CISC: A task may be completed in a single cycle, as instructions may be more complex than individual instructions in RISC."

The way I understand it from this definition is as so; if a program wanted to multiply the contents of the accumulator by two, a CISC processor may just use MULT 2, and as this is an instruction available to it, it completes it in one cycle.

A RISC processor on the other hand, may have to use a number of simpler instructions, to achieve the same result (i.e. ADD 15, SUB 12 etc.). Because it needs multiple instructions, it therefore takes multiple cycles.



Here's where it is a bit confusing, when asked to "Name 3 features of the CISC architecture", the mark scheme says:

"Uses complex instructions, each of which may take multiple cycles."

Wait, what? This completely undermines the first example. If the complex instructions take more cycles to complete than simple instructions, then both the RISC and the CISC processors will use multiple cycles in carrying out the MULT command.



Is the key here just to use weasel words such as "may"? I hate that there are so many contradictions in the mark-schemes.
It seems important that you have to distinguish between task and instruction, otherwise you may get caught out for describing the wrong thing.
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Tamago2474
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I know what you mean, there is quite a big contradiction. A practice paper I did had the question: Describe the relationship between RISC instructions and processor cycles. And the same question but for CISC instructions.

The mark scheme said for RISC: One instruction may be many cycles on a RISC.
And for CISC: Each command takes one cycle.

This goes directly against what I've learnt from textbooks and on the internet so I'm hoping that it is wrong as the practice paper wasn't from OCR and it had some other mistakes in it too. I'm just going to go with what I've learnt to be correct in the exam if it comes up.

Good luck!
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Joinedup
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(Original post by Tamago2474)
I know what you mean, there is quite a big contradiction. A practice paper I did had the question: Describe the relationship between RISC instructions and processor cycles. And the same question but for CISC instructions.

The mark scheme said for RISC: One instruction may be many cycles on a RISC.
And for CISC: Each command takes one cycle.

This goes directly against what I've learnt from textbooks and on the internet so I'm hoping that it is wrong as the practice paper wasn't from OCR and it had some other mistakes in it too. I'm just going to go with what I've learnt to be correct in the exam if it comes up.

Good luck!
Probably you're confused about the difference between clock cycles and fetch-decode-execute cycles.

common CISC cpu e.g. 8086 takes several clock cycles to complete one fetch-decode-execute cycle... it varied on the amount of work required to complete the instruction, might be up to 10 clock cycles.

common RISC cpu e.g. ARM takes one clock cycle to complete one fetch-decode-execute cycle... it uses an optimization called pipelining to look ahead and start decoding the next instructions while it's executing the current instruction.
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