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    I need to design a modulo 6* d type asynchronous down counter in which gated outputs reset the bistables after the appropiate count is achieved.

    The drawing shows a three stage counter which i can modify.

    A modulo 6* needs to count down 5,4,3,2,1,0 then resets back to 5,4,3,2,1, 0 etc

    I can get it to start at 5 and count down to zero but it always resets back to 7.

    Please help as its doing my head in

    Thanks
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    (Original post by Mechynick)

    I need to design a modulo 6* d type asynchronous down counter in which gated outputs reset the bistables after the appropiate count is achieved.
    This is electronics rather than maths. It would probably be better moved to the physics forum.
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    Sorry new to the forum
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    (Original post by Mechynick)
    Sorry new to the forum
    Thanks
    You probably want to send a message to Zacken or someone to have it moved.

    I'm afraid that it's been so long since I've done any digital electronics that I'd have to crack open the textbooks to be able to analyse the circuit. I think that uberteknik on the physics forums is more up-to-date with this kind of stuff though.
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    Ive posted it on there now but no joy so far
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    (Original post by Mechynick)
    Ive posted it on there now but no joy so far
    Can't say I'm familiar with this, but in case this is of some value.

    After the counter reaches 0, you want the next state to be 5, i.e. 101 binary.
    So, the input to the second d-type flip flop needs to be forced to 0, but only when the Q outputs are 0,0,0.

    So, interrupt the feedback on the second stage, and AND it, with the three Q outputs OR'ed together.

    So, when counter reaches zero, their OR'd sum will be zero, AND returns zero, and the input at D will be zero.

    When counter is non-zero, OR'd sum is non-zero, and the AND gate will pass through the value from the QN output.

    I imaginve this would be similar to "starting at 5" which you've already sorted.
 
 
 
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