BuddharajuS01
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What are the key steps of the fetch decode execute cycle?
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JackMoseley
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I’m not sure what level (gcse or a level) you’re wanting but this is how we were taught it at a level:

MAR <— PC
MAR —> Main Memory (done via the address bus)
MBR <— Main Memory (done via the data bus)
PC <— PC 1 (really it is increased to the next memory location but you just need to know it’s increased)
CIR <— MBR
Repeat whilst instruction is executed

MAR = Memory Address Register
PC = Program Counter
Main Memory = RAM
MBR = Memory Buffer Register
CIR = Current Instruction Register

Hope this makes sense? I’m happy to explain this if you would like me to.
Last edited by JackMoseley; 2 years ago
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