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Verilog : It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to

Verilog : It's supposed to be a MOD10 counter but it counts from 0 to 9 and resets to 4, why?? Please give me the solution as a code and explaination for it if possible.

module TFF (clk, clr, t, q); input clk, clr, t; output reg q; always @(posedge clr or negedge clk) begin if (clr) q <= 0; // Clear or reset the flip-flop else begin if (!t) q <= q; // Maintain the state when T = 0 else q <= ~q; // Toggle the output when T = 1 end endendmodule module MOD10_TB(); reg clk, clr; wire [3:0] q; // Instantiate the MOD10 module MOD10 uut (clk, clr, q); // Clock signal generation (50% duty cycle) initial begin clk = 0; forever #5 clk = ~clk; // Toggle clock every 5 time units end // Reset logic and test sequence initial begin clr = 1; // Reset active #10 clr = 0; // Deactivate reset after 10 time units #110 $finish; // End simulation after 110 time units endendmodule

It's supposed to be a MOD10 counter, so I expected for it to count from 0 to 9 and reset to 0 again but it counts from 0 to 9 and resets to 4.

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Darokcamper

CFBR

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