quick! Can I have some help please?

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Brackets
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#1
I've got a2 computing tommorow (Edexcel), and in my revision guide it says I have to know the
difference between a RISC (Reduced instruction set computer) and a CISC (Complex instruction set
computer), although it doesn't seem like I need to know it in too much detail.

Can some kind person please give me a brief overview on the two, and under what conditions is one
better than the other?

And secondly, whats the difference between base register addressing and indexed addressing? Again,
in my revision guide it doesn't explain it too well, and all the textbooks I have don't even state
that there is any difference.

I'm sure I'll post more questions up as I realise I can't find the answers
[q1][/q1]

Thanks in advance.

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Richard Hayden
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#2
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[q1]> I've got a2 computing tommorow (Edexcel), and in my revision guide it says[/q1]
I
[q1]> have to know the difference between a RISC (Reduced instruction set computer) and a CISC (Complex[/q1]
[q1]> instruction set computer), although it[/q1]
doesn't
[q1]> seem like I need to know it in too much detail.[/q1]

The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible.
This is achieved by building processor hardware that is capable of understanding and executing a
series of operations. For example, for adding two numbers together, a CISC processor would come
prepared with a specific instruction. In the case of x86 processors, this instruction is 'add'.

Here's an example of this instruction:

add eax, 12

This instruction loads the value in the register eax and the value 12 into the execution unit, and
then adds them together, storing the result back into the register eax. This is all achieved through
one instruction. This is known as a complex instruction, as it operates directly on registers and
memory and does not require the programmer to call any specific loading or storing instructions
(such as, mov etc.).

This instruction can also take many different forms and addressing modes, for example:

add eax, [ebx]

This instruction would load the value stored in eax and the value stored in the memory
location pointed at by ebx into the execution unit and then add them together, storing the
result back into eax.

This is another characteristic of a complex instruction, they can deal with different sources of
data and different addressing modes, all using the same base instruction.

These complex instructions closely resemble commands in a higher level language. For example,
considering the instruction, add eax, 12 and letting a = eax, then that instruction closely
resembles the following C line of code:

a = a + 12

One of the primary advantages of this system is that the compiler has to do very little work to
translate a high-level language statement into assembly. Because the length of the code is
relatively short, very little RAM is required to store instructions. The emphasis is put on building
complex instructions directly into the hardware.

RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the
'add' instructions described above could be divided into seperate commands, so that each command
only takes one clock cycle to execute. RISC processors also have a smaller instruction set, as tasks
are generally written as collections of the basic instructions, whereas with CISC there are single
instructions available to complete most simple tasks.

At first, this may seem like a much less efficient way of completing the operation. Because there
are more lines of code, more RAM is needed to store the assembly level instructions. The compiler
must also perform more work to convert a high-level language statement into code of this form.
However, there are also advantages to RISC architectures; the following table shows the advantages
and disadvantages of each architecture:

Advantages + Disadvantages of CISC:

Easier to translate from HLLs to assembly. Smaller code sizes. Harder to translate from assembly to
machine code. Requires a higher number of transistors; cost.

Advantages + Disadvantages of RISC:

Harder to translate from HLLs to assembly. Larger code sizes. Easier to translate from assembly to
machine code. Requires a lower number of transistors; cost Decreasing prices of RAM, means that the
fact that RISC uses more memory is not so important. Lower amount of software support at current.

Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is primarily
due to advancements in other areas of computer technology. The price of RAM has decreased
dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only
$6 (when adjusted for inflation). Compiler technology has also become more sophisticated, so that
the RISC use of RAM and emphasis on software has become ideal, although the market hold of x86
architecture processors, such as AMD's and Intel's processors, mean that it is unlikely, at least
for the moment, that RISC processors will take a substantial market share.

[q1]> And secondly, whats the difference between base register addressing and indexed addressing? Again,[/q1]
[q1]> in my revision guide it doesn't explain it too well, and all the textbooks I have don't even state[/q1]
[q1]> that there is any difference.[/q1]

I usually call both of these addressing modes under one name; register indirect addressing modes.

They both take the form:

mov ebx, [register]

Where register is a general purpose register. This would copy the data held at the memory location
pointed to by 'register' into the ebx register.

Both base register addressing and indexed addressing are functionally equivalent. The only
difference is that for base register addressing modes, the (e)ax. (e)bx, (e)bp, (e)dx, etc.
registers are used as pointers and indexed addressing is where you use the (e)si or (e)di registers
as pointers. This is the only difference.

--

Richard Hayden ([email protected])

Webmaster: http://www.dx-dev.com

"Ich suche die Antworten, wie viele Leute vor und nach mir. Ich stelle Fragen, aber ich akzeptiere
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"Richard Hayden" <[email protected]> wrote in message news:[email protected]...

<snip great help>

Thanks a lot, thats really helped me understand

Thanks again

(now I just hope it comes in handy tommorow )

--
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Gaurav Sharma
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#4
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"Brackets" <[email protected] com> wrote in message
news:[email protected]...
[q1]>[/q1]
[q1]> "Richard Hayden" <[email protected]> wrote in message[/q1]
[q1]> news:[email protected]...[/q1]
[q1]>[/q1]
[q1]> <snip great help>[/q1]
[q1]>[/q1]
[q1]> Thanks a lot, thats really helped me understand [/q1]
[q1]>[/q1]
[q1]> Thanks again[/q1]
[q1]>[/q1]
[q1]> (now I just hope it comes in handy tommorow )[/q1]
[q1]>[/q1]
[q1]>[/q1]
[q1]> --[/q1]
[q1]> Alex Studders Greggers Brackets[/q1]
[q1]>[/q1]
[q1]>[/q1]
It still confuses me on how they could ask for something so deep in an A-level exam, at Imperial I
don't think they'd expect first year comp scis to know that, well I didn't know anyway. Also,
Richard Hayden, why does your name sound familiar?

G.Sharma.
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#5
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"Gaurav Sharma" <[email protected]> wrote in message
news:[email protected]...
[q1]>[/q1]
[q1]> "Brackets" <[email protected] com> wrote in message[/q1]
[q1]> news:[email protected]...[/q1]
[q2]> >[/q2]
[q2]> > "Richard Hayden" <[email protected]> wrote in message[/q2]
[q2]> > news:[email protected]...[/q2]
[q2]> >[/q2]
[q2]> > <snip great help>[/q2]
[q2]> >[/q2]
[q2]> > Thanks a lot, thats really helped me understand [/q2]
[q2]> >[/q2]
[q2]> > Thanks again[/q2]
[q2]> >[/q2]
[q2]> > (now I just hope it comes in handy tommorow )[/q2]
[q2]> >[/q2]
[q2]> >[/q2]
[q2]> > --[/q2]
[q2]> > Alex Studders Greggers Brackets[/q2]
[q2]> >[/q2]
[q2]> >[/q2]
[q1]> It still confuses me on how they could ask for something so deep in an A-level exam, at Imperial I[/q1]
[q1]> don't think they'd expect first year comp scis to know that, well I didn't know anyway. Also,[/q1]
[q1]> Richard Hayden, why does your name sound familiar?[/q1]

Well, although my revision guide only mentions it briefly, meaning it could be something we are
only expected to know in very little detail, it being a revision guide, mentions everything only
very briefly.

Todays lesson kids: Don't try and learn the years work from one revision guide.

--
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Richard Hayden
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#6
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[q1]> It still confuses me on how they could ask for something so deep in an A-level exam, at Imperial I[/q1]
[q1]> don't think they'd expect first year comp scis to know that, well I didn't know anyway.[/q1]

I've only done AS-level computing (A-level, next year), but computer-programming is a pretty
obsessive hobby of mine.

[q1]> Also, Richard Hayden, why does your name sound familiar?[/q1]

I don't know, I can't say yours rings any immediate bells, but maybe we've met in a newsgroup
somewhere...

[q1]>[/q1]
[q1]> G.Sharma.[/q1]

--

Richard Hayden ([email protected])

Webmaster: http://www.dx-dev.com

"Ich suche die Antworten, wie viele Leute vor und nach mir. Ich stelle Fragen, aber ich akzeptiere
nichts, alle müssen bewiesen werden."

---
Outgoing mail from Richard Hayden is certified Virus Free. Checked by AVG anti-virus system
(http://www.grisoft.com). Version: 6.0.371 / Virus Database: 206 - Release Date: 13/06/2002
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